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Espressif Systems /ESP32-C2 /SYSTEM /PERIP_CLK_EN0

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Interpret as PERIP_CLK_EN0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (SPI01_CLK_EN)SPI01_CLK_EN 0 (UART_CLK_EN)UART_CLK_EN 0 (UART1_CLK_EN)UART1_CLK_EN 0 (SPI2_CLK_EN)SPI2_CLK_EN 0 (I2C_EXT0_CLK_EN)I2C_EXT0_CLK_EN 0 (LEDC_CLK_EN)LEDC_CLK_EN 0 (TIMERGROUP_CLK_EN)TIMERGROUP_CLK_EN 0 (UART_MEM_CLK_EN)UART_MEM_CLK_EN 0 (APB_SARADC_CLK_EN)APB_SARADC_CLK_EN 0 (SYSTIMER_CLK_EN)SYSTIMER_CLK_EN 0 (ADC2_ARB_CLK_EN)ADC2_ARB_CLK_EN

Description

peripheral clock gating register

Fields

SPI01_CLK_EN

Set 1 to enable SPI01 clock
UART_CLK_EN

Set 1 to enable UART clock
UART1_CLK_EN

Set 1 to enable UART1 clock
SPI2_CLK_EN

Set 1 to enable SPI2 clock
I2C_EXT0_CLK_EN

Set 1 to enable I2C_EXT0 clock
LEDC_CLK_EN

Set 1 to enable LEDC clock
TIMERGROUP_CLK_EN

Set 1 to enable TIMERGROUP clock
UART_MEM_CLK_EN

Set 1 to enable UART_MEM clock
APB_SARADC_CLK_EN

Set 1 to enable APB_SARADC clock
SYSTIMER_CLK_EN

Set 1 to enable SYSTEMTIMER clock
ADC2_ARB_CLK_EN

Set 1 to enable ADC2_ARB clock

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data